1. Field of the Invention
The present invention relates to interleaving of a memory bank, and more particularly, to a method and apparatus of interleaving a memory bank in a multi-layer bus system.
2. Description of the Related Art
A structure of a bus in an embedded System-on-Chip (SoC) depends on the type of a processor installed in the SoC. For instance, an Advanced Microcontroller Bus Architecture (AMBA) Advanced High-performance Bus (AHB) is used when an ARM processor is included in a SoC. In general, the performance of the SoC varies according to factors, such as the type of a processor, the performance of software and the performance of a bus provided. When a piece of hardware is manufactured using the SoC, connection with a memory or memories is required. The hardware performance is largely affected by that of the memory. Generally, a Synchronous Dynamic Random Access Memory (SDRAM) or a Double Data Rate (DDR) memory is used as the memory. Accordingly, a delay in data transmission may occur based on the performance of the memory.
When a slave device, such as an SDRAM, is shared and simultaneously accessed by a plurality of master devices, such as a processor or a Direct Memory Access (DMA) unit, the performance of a system is not remarkably influenced by the type of bus used. In this case, the performance of the system is affected only by a response delay of the bus. Generally, the AHB bus, for example, is a bus with good performance, which has a clock response delay of 0.
Moreover, when the SDRAM is used as a slave device and reading and/or writing data is performed by accessing the SDRAM, it is possible to reduce a response delay caused when the SDRAM is continuously accessed by using bank interleaving. Bank interleaving is a function of improving speed of data processing by dividing a storage space of a memory into several banks, for example, dividing the storage space of the memory into rooms for storing and/or processing data, and allowing the several banks to process data in response to a processing command.
However, it is impossible to use bank interleaving for an SDRAM connected with an AHB system bus, where sequence of commands and responses to commands are predetermined and, thus, a large delay in data transmission becomes unavoidable.